Bangkok

Tomoaki Sato

Department of Management and Information Science*
School of Economics, Hokusei Gakuen University

* Effective April 2027, the department will adopt this new name, and the curriculum will also be revised.

Academic Profiles

Biography

2001: Completed the doctoral program, Graduate School of Engineering, Tohoku University; Ph.D. in Engineering　
2001–2005: Assistant Professor, Department of Social Information, Faculty of Social Information, Sapporo Gakuin University
2005–2017: Associate Professor, Computing and Networking Center, Hirosaki University
2017–March 2027: Professor, Department of Management Information, School of Economics, Hokusei Gakuen University
April 2027–present: Professor, Department of Management and Information Science, School of Economics, Hokusei Gakuen University

Research

Research on machine learning-based intrusion prevention systems and computer architectures that enable high-speed, low-power processing.
We explore FPGA–ASIC co-design and reconfigurable circuit technologies for applications in IoT and embedded devices.
(Computer architecture; VLSI design; reconfigurable computing; embedded systems; IoT; computer networks; and cybersecurity)

This research is conducted in collaboration with King Mongkut’s Institute of Technology Ladkrabang and Chulalongkorn University in Thailand.

Grants-in-Aid for Scientific Research (KAKENHI)

Principal investigator for all projects; conducted independently

Peer-Reviewed Publications

  1. T. Sato, A. Murakami, S. Chivapreecha and P. Moungnoul, “A Low-Latency Fixed-Function FPGA Architecture for Neural Network Primitives,” 2026 14th International Electrical Engineering Congress (iEECON), pp. 1-6, 2026, doi: 10.1109/iEECON68065.2026.11707107.
  2. T. Sato, A. Murakami, S. Chivapreecha and P. Moungnoul, “A Binary Tree-Based Routing-Only Architecture for RTL-Designed FPGAs Using Addressable Configuration Memory,” Proc. of ECTI-CON 2026, May 2026, doi: 10.1109/ECTI-CON68836.2026.11608576.
  3. T. Sato, A. Murakami, S. Chivapreecha and P. Moungnoul, “Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration,” 2025 13th International Electrical Engineering Congress (iEECON), pp. 1-6, May 2025, doi: 10.1109/iEECON64081.2025.10987880.
  4. S. Chivapreecha, P. Suwannawach and T. Sato, “Amplitude stabilization of frequency-tunable biquad digital oscillator using zero-input response analysis,” Proc. of SPIE, vol. 13518, pp. 135180F-1–135180F-10, Feb. 2025.
  5. T. Sato, A. Murakami, S. Chivapreecha and P. Moungnoul, “Application-optimized FPGAs design using RTL-designed FPGAs architectures,” Proc. of SPIE, vol. 13518, pp. 135180Q-1–135180Q-8, Feb. 2025.
  6. A. Murakami, M. Toyoshima and T. Sato, “CAD development and routing analysis for RTL-designed FPGAs,” Proc. of SPIE, vol. 13518, pp. 135180U-1–135180U-10, Feb. 2025.
  7. T. Sato, Y. Hayashihara, S. Yokota, S. Chivapreecha and P. Moungnoul, “Optimal Number of Wires for Circuits on RTL-Designed FPGAs,” Proc. of iEECON 2024, pp. P03714.1–P03714.4, Mar. 2024.
  8. T. Sato, K. Higuchi, S. Chivapreecha and P. Moungnoul, “Proposal of a High-speed and Low-power Architecture for Entropy Coding Processing to Achieve Highest Compression Rate,” Proc. of the 1st ECTI UEC Workshop on AI and Applications, pp. 72-73, Sep. 2019.
  9. T. Sato, S. Chivapreecha, K. Higuchi and P. Moungnoul, “Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing,” Proc. of ISCIT 2018, pp. 204-207, Sep. 2018.
  10. U. Chaiwongkhan, S. Matathong, T. Sato and P. Moungnoul, “Comparison of Frequency ReuseSchemes for LTE Micro-Macro Cells,” Proc. of ECTI-CON 2018, pp. 214-217, Jul. 2018.
  11. T. Sato, S. Chivapreecha, K. Higuchi and P. Moungnoul, “Automatc Fine-Tuning of Wave-Pipelined Circuits and Development of Route Analysis Tool for It,” Proc. of ITC-CSCC 2018, pp. 118-121, Jul. 2018.
  12. P. Kongsawat, S. Chivapreecha and T. Sato, “Quality Assessment of Thai Rice Kernels Using Low Cost Digital Image Processing System,” Proc. of IWAIT 2018, pp. 207.1-207.4, Jan. 2018.
  13. T. Sato, S. Chivapreecha, K. Higuchi and P. Moungnoul, “A Detection Method of Web Authentication Problems for Mobile Devices Corresponding to IEEE 802.11ac,” Proc. of IWAIT 2018, pp. 221.1-221.4, Jan. 2018.
  14. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “A Circuit Design for IEEE 802.11ac by ASIC-FPGA Co-Design,” Proc. of ISMAC 2017, pp. 89-92, Aug. 2017.
  15. P. Moungnoul and T. Sato, “Investigated of DOCSIS Mesurement Results for Performance Improvement,” Proc. of ISMAC 2017, pp. 195-198, Aug. 2017.
  16. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “RCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined Operation,” ECTI Transactions CIT, vol. 11, no. 1, pp. 11-20, May 2017.
  17. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “Throughput of a Firewall Unit on FPGAs developed by the RTL Design Methodology,” Proc. of iEECON 2017, vol. 2, pp. 423-426, Mar. 2017.
  18. K. Ogiwara, K. Higuchi, T. Sato, S. Premrudeepreechacharn and K. Jirasereeamornkul, "Approximate 2-Degree-of-Freedom Digital Control of an Interleaved Low Voltage DC-DC Buck Converter," Proc. of iEECON 2017, vol. 1, 13-16, Mar. 2017.
  19. S. Chivapreecha, N. Ronnaronglit and T. Sato, “Chaos in Digital Filter for Digital Image Encryption,” Proc. of IWAIT2017, pp. 6C.5.1-6C.5.4, Jan. 2017.
  20. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “An FPGA Architecture for ASIC-FPGA Co-Design to Streamline Processing of IDSs,” Proc. of CTS 2016, pp. 412-417, Oct. 2016.
  21. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “Designing a Firewall Unit on the FPGA Composed of Selectors,” Proc. of SISA 21016, pp. 53-58, Sept. 2016.
  22. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi, “Proposal of an Automatic Running AP in Wireless LANs for the Maximization of the Throughput,” Proc. of CreTech 2016, pp. 9-11, Aug. 2016.
  23. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “RCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined Operation, Proc. of ECTI-CON 2016, pp. 1251.1-1251.6, Jun. 2016.
  24. K. Hanabusa, K. Higuchi, T. Sato and K. Jirasereeamornkul, “Approximate 2-Dgree-of-Freedom Control of a Class-D Amplifier Using FPGA,” Proc. of ECTI-CON 2016, pp. 1152.1-1152.6, Jun. 2016.
  25. T. Sato, S. Chivapreecha and P. Moungnoul, “A Connection Block Implemented in the RTL Design for Delay Time Equalization of Wave-Pipelining,” Journal of Systemics, Cybernetics and Informatics, vol. 14, no. 1, pp. 49-54, Apr. 2016.
  26. N. Ronnaronglit, S. Chivapreecha and T.Sato, “An Improved Digital Image Encryption Using Chaos in Digital Filter,” Proc. of ISMAC 2015, pp. 297-301, Sept. 2015.
  27. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi, “Optimization of Radio Waves of Wi-Fi LANS for Universities,” Proc. of CreTech 2015, p. 22, Aug. 2015,
  28. T. Sato, S. Chivapreecha and P. Moungnoul, “Fine-Tuning of Wave-Pipelines on FPGAs Developed by the RTL Design,” Proc. of ECTI-CON 21015, pp. 1230.1-1230.6, Jun. 2015.
  29. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi “Proposal of the security log collection method of public Wi-Fi services on private IPv4 address spaces utilizing Raspberry Pi,” Proc. of ICESIT 2015, pp. 6-7, Jun. 2015.
  30. T. Sato, S. Chivapreecha and P. Moungnoul, “The Potential of Routes Configured with the Switch Matrix by RTL,” Applied Mechanics and Materials Journal, vol. 781, pp. 189-192, May 2015.
  31. T. Sato, S. Chivapreecha and P. Moungnoul, “Wiring Control by RTL Design for Reconfigurable Wave-Pipelined Circuits,” Proc. of APSIPA ASC 2014, pp. WP1-3-1-WP1-3-6, Dec. 2014.
  32. T. Sato, S. Chivapreecha and P. Moungnoul, “Design and Analysis of Crossbar Switch Circuits for Reconfigurable Wave-Pipelined Circuits,” Proc. of CreTech 2014, pp. 12-15, Aug. 2014.
  33. T. Sato, S. Chivapreecha and P. Moungnoul, “Evaluation of Logic Blocks for Reconfigurable Wave-Pipelined Circuits with 45nm CMOS Technology,” Proc. of ITC-CSCC2014, pp. 464-465, Jul. 2014.
  34. T. Sato, S. Chivapreecha and P. Moungnou, “A Crossbar Switch Circuit Design for Reconfigurable Wave-Pipelined Circuits,” Proc. of WMSCI 2014, vol. II, pp. 200-205, Jul. 2014.
  35. T. Sato, P. Moungnoul, S. Chivapreecha and K. Higuchi, “Performance Estimates of an Embedded CPU for High-Speed Packet Processing,” Proc. of ECTI-CON 2014, pp.1298.1-1298-5, May 2014.
  36. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, “Evaluations of Waved-Shift Registers for Multiplexed Bus,” Proc. of iEECON2014, pp. 109.1-109.4, Mar. 2014.
  37. Y. Adachi, K. Higuchi, T. Sato and K. Chamnongthai, “Robust Digital Control for Interleaved PFC Boost Converters Using an Approximate 2DOF Current Controller,” ECTI Transactions EEC, vol. 12, no. 1, pp. 37-43, Feb. 2014.
  38. T. Sato, S. Chivapreecha and P. Moungnoul, “A Logic Block for Wave-Pipelining,” Proc. of IMETI 2013, pp. 130-134, Jul. 2013.
  39. T. Sato and P. Moungnoul, “Hardware Amount Evaluation of the Improved WEP on an FPGA,” Proc. of ECTI-CON 2013, pp. 1760.1-1760.6, May 2013.
  40. Y. Adachi, Y. Fukaishi, K. Higuchi, T. Sato and K. Chamnongthai, “Robust Digital Control for Interleave PFC Boost Converter,” Proc. of The 18th International Symposium on ARTIFICIAL LIFE AND ROBOTICS, p. 185, Feb. 2013.
  41. Y. Adachi, K. Higuchi, T. Kajikawa, T. Sato and K. Chamnongthai, “Digital PI control for interleave PFC boost converter,” Proc. of The 18th International Symposium on ARTIFICIAL LIFE AND ROBOTICS, p. 163, Feb. 2013.
  42. M. Fukase, K. Ichinohe, K. Narita, T. Takaki, N. Mimura, T. Sato and A. Kurokawa, “Development of a Next Generation Ubiquitous Processor Chip,” ECTI Transactions CIT, vol. 6, no. 2, pp. 120-127, Nov. 2012.
  43. T. Sato, P. Moungnoul and M. Fukase, “Delay Time Analysis of Reconfigurable Firewall Unit,” Journal of Systemics, Cybernetics and Informatics, vol. 10, no. 5, pp. 80-84, Oct. 2012.
  44. T. Sato, P. Moungnoul and M. Fukase, “Packet Filtering Circuits for Smart Phones,” Proc. of The 16th World Multi-Conference on Systemics, Cybernetics and Informatics, vol. II, pp. 5-9, Jul. 2012.
  45. M. Fukase, K. Ichinohe, N. Mimura, K. Narita, T. Takaki and T. Sato, “VLSI Implementation With Double Cipher and Media Processing for Ad-Hoc Network,” Proc. of ECTI-CON 2012, pp. 1162-1-1162-4, May 2012.
  46. M. Fukase and T. Sato, “Double Cipher Implementation in a Ubiquitous Processor Chip,” American Journal of Computer Architecture, vol.1 no.1 pp. 6-11, May 2012.
  47. T. Sato, P. Moungnoul and M. Fukase, “Throughput Evaluation of Improved WEP Processing on a Mobile Processor,” Proc. of 1st International Symposium on Technology for Sustainability, pp. 325-328, Jan. 2012.
  48. M. Fukase, H. Uchiumi, K. Narita, T. Takaki, N. Mimura, K. Ichinohe, T. Sato and A. Kurokawa, “Development of a Next Generation Ubiquitous Processor Chip,” Proc. of the 18th IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 225.1-225.4, Dec. 2011.
  49. M. Fukase, N. Mimura, K. Narita, T. Takaki, H. Uchiumi, T. Ishihara and T. Sato, “Evaluation for the Power Conscious Optimum Design of a Ubiquitous Processor,” Proc. of the 4th International Multi-Conference on Engineering and Technological Innovation, vol. II, pp. 104-108, Jul. 2011.
  50. M. Fukase, H. Uchiumi, T. Ishihara, N. Mimura, K. Narita, T. Takaki and T. Sato, “Double Cipher Implementation in a Ubiquitous Processor Chip,” Proc. of ECTI-CON 2011, pp.125-128, May 2011.
  51. T. Sato, P. Moungnoul and M. Fukase, “Compatible WEP Algorithm for Improved Cipher Strength and High-Speed Processing,” Proc. of ECTI-CON 2011, pp. 401-404, May 2011.
  52. M. Fukase, T. Ishihara, H. Uchium and T. Sato, “Design and Evaluation of a Waved MFU,” Proc. of APSIPA ASC 2010, p. 70, Dec. 2010.
  53. M. Fukase, H. Uchiumi, T. Ishihara and T. Sato, “Impact of Using a Double Cipher Scheme on the Implementation of a Particular Ubiquitous Processor,” Proc. of ISCIT 2010, pp. 821-826, Oct. 2010.
  54. M. Fukase and T. Sato, “A Ubiquitous Processor Built-in a Waved Multifunctional Unit,” ECTI Transactions CIT, vol. 4, no. 1, pp. 1-7, May 2010.
  55. T. Sato, K. Ito, K. Saito, P. Moungnoul and M. Fukase, “Development of a shift register for Firewall Circuits by Wave-Pipelined Operations,” Proc. of ICT2010, pp. w4c-1-1-w4c-1-4, Aug. 2010.
  56. T. Sato, P. Moungnoul and M. Fukase, “Power Control Scheme for H-HIPS in Mobile Communications,” Proc. of ICT2010, pp. s3-3-1-s3-3-4, Aug. 2010.
  57. P. Moungnoul, A. Sopin and T. Sato, “Performance of IR-UWB PSM and BPM over S-V Channel Model,” Proc. of ICT2010, pp. W2A-1-1-W2A-1-4, Aug. 2010.
  58. M. Fukase and T. Sato, “H/S Collaborative Development of a Ubiquitous Processor Free from Instruction Scheduling and Pipeline Disturbance,” Proc. of 9the IEEE/ACIS International Conference on Computer and Information Science, pp. 57-62, Aug. 2010.
  59. T. Sato, P. Moungnoul, K. Saito and M. Fukase, “Development of a WiMAX Processor by Using a CPLD,” Proc. of IMETI2010, vol. II, pp. 128-133, Jun. 2010.
  60. M. Fukase, A. Yokoyama, T. Ishihara, H. Uchiumi and T. Sato, “Wave Degree versus Dominant Characteristics of a Waved Multifunctional Unit,” Proc. of IMETI2010, vol. II, pp. 164-168, Jun. 2010.
  61. P. Moungnoul N. Worawatjirakul S. Junnapiya U. Thongrak J. Chanwutitum and T. Sato, “TCP Performance Improvement for Wireless Access using Cross-Layer MIMO Adaptive Modulation,” Proc. of ICESIT2010, pp. 104.1-104.6, Feb. 2010.
  62. P. Moungnoul, J. Jarassriwilai, U. Thongrak, N. Panitjaroen and T. Sato, “MIMO Adaptive Modulation with Cross-Layer Model of Queuing over Nakagami Fading,” Proc. of ICESIT2010, pp. 92.1-92.6, Feb. 2010.
  63. N. Panitjaroen, P. Moungnoul, T. On-In, J. Chanwutitum and T. Sato, “Performance Improvement of Satellite Channel with Combine Ionosphere Scintillation and Small Scale Fading using Adaptive Modulation,” Proc. of ICESIT2010, pp. 90.1-90.4, Feb. 2010.
  64. T. Sato, P. Moungnoul, k. Saito and M. Fukase, “Wave-Pipelined CRC Circuits for Wireless Broadband Systems Based on W-CDMA,” Proc. of ICESIT2010, pp. 100.1-100.4, Feb. 2010.
  65. M. Fukase and T. Sato, “Exploring the Optimum Buffer Size of an Emerging Stream Cipher Engine,” ECTI Transactions EEC, vol. 8, no. 1, pp. 53-58, Feb. 2010.
  66. M. Fukase, R. Murakami and T. Sato, “Design and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor,” Proc. of ASP-DAC 2010, pp.375-376, Jan. 2010.
  67. T. Sato, S. Imaruoka and M. Fukase, “Verifying Firewall Circuits by Wave-Pipelined Operations,” Proc. of IEEE TENCON 2009, pp. WED3.P.14.1 -WED3.P.14.6, Nov. 2009.
  68. M. Fukase and T. Sato, “Performance Evaluation of an Emerging Stream Cipher Engine,” Proc. of APSIPA ASC 2009, pp. 583-588, Oct. 2009.
  69. M. Fukase, H. Uchiumi, T. Ishihara, Y. Osumi and T. Sato, “Cipher and Media Possibility of a Ubiquitous Processor,” Proc. of ISCIT 2009, pp. 343-347, Sep. 2009.
  70. M. Fukase and T. Sato, “A Waved Multifunctional Unit on Account of Multimedia Mobile Computing,” Proc. of WMSCI 2009, vol. III, pp. 86-91, Jul. 2009.
  71. T. Sato, S. Imaruoka and M. Fukase, “Hardware-Based IPS for Embedded Systems,” Proc. of WMSCI 2009, vol. III, pp. 74-79, Jul. 2009.
  72. M. Fukase, A. Yokoyama and T. Sato, “A Ubiquitous Processor Embedded with Progressive Cipher Pipelines,” Proc. of GLSVLSI’09, pp. 381-384, May 2009.
  73. M. Fukase, Y. Ohsumi and T. Sato, “Exploring the Optimum Buffer Size of an Emerging Stream Cipher Engine,” Proc. of ECTI-CON 2009, pp. 607-610, May 2009.
  74. T. Sato, S. Imaruoka and M. Fukase, “System-Level Control for Low-Power Consumption on Winny Detection System.” Proc. of ICESIT2009, pp. 10-14, Feb. 2009.
  75. T. Sato, S. Imaruoka and M. Fukase, “Reconfigurable Firewall Unit by Wave-Pipelined Operations,” Proc. of ISPACS 2008, pp. 449-452, Feb. 2009.
  76. M. Fukase, K. Noda and T. Sato, “Emerging Hardware Cryptography and VLSI Implementation,” Proc. of ISPACS 2008, pp. 445-448, Feb. 2009.
  77. M. Fukase, K. Noda, A. Yokoyama and T. Sato, “Design and Chip Implementation of the Ubiquitous Processor HCgorilla,” Proc. of ASP-DAC, pp. 129-130, Jan. 2009.
  78. T. Sato, S. Imaruoka and M. Fukase, “FPGA Implementation of Winny Packets Detection for Mobile Computing,” Proc. of ISCIT2008, pp. 204-209, Oct. 2008.
  79. M. Fukase and T. Sato, “A Ubiquitous Processor Free from Instruction Scheduling,” Proc. of ISCIT2008, pp. 75-80, Oct. 2008.
  80. T. Sato, S. Imaruoka, M. Fukase, FPGA Implementation of a Winny Detection Method for Campus Networks, Journal for Academic Computing and Networking, no. 12, pp. 68-74, Sep. 2008.
  81. M. Fukase and T. Sato, “Compilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor,” Journal of Systemics, Cybernetics and Informatics, vol. 5, no. 6, pp. 13-21, Sep. 2008.
  82. M. Fukase and T. Sato, “Compact FPU Design and Embedding in a Ubiquitous Processor for Multimedia Performance Enhancement,” ECTI-EEC Trans. vol. 6, no. 2, pp. 79-85, Aug. 2008.
  83. T. Sato, K. Kikuchi, S. Imaruoka and M. Fukase, “DoS Attack Analysis for H-HIPS,” Proc. of IMETI 2008, vol. II, pp. 110-115, Jul. 2008.
  84. M. Fukase and T. Sato, “Development of Parallelizing Compilers of a Ubiquitous Processor,” Proc. of WMSCI2008, vol. II, pp. 220-225, Jul. 2008.
  85. M. Fukase, K. Noda, A. Yokoyama and T. Sato, “Enhancing Multimedia Processing by Wave-Pipelining Integer Units and Floating Point Units in Whole,” Proc. of ECTI-CON 2008, pp. II-681-II-684, May 2008.
  86. T. Sato, K. Kikuchi, S. Imaruoka and M. Fukase, “Low-Power Scheme of Portscan Detection Unit by Using Embedded Technology,” Proc. of ICESIT2008, pp. 122-125, Feb. 2008.
  87. M. Fukase, H. Takeda, K. Noda, A. Yokoyama and T. Sato, “Ad-hoc Cipher by a Ubiquitous Processor,” Proc. of ICESIT 2008, pp. 118-121, Feb. 2008.
  88. M. Fukase and T. Sato, “A Stream Cipher Engine for Ad-hoc Security,” Proc. of CIS’2007, pp. 902-906, Dec. 2007.
  89. M. Fukase, K. Noda, H. Takeda and T. Sato, “Multimedia Performance of a Ubiquitous Processor,” Proc. of ISCIT2007, pp. 1464-1469, Oct. 2007.
  90. M. Fukase, H. Takeda and T. Sato, “Hardware/Software Co-Design of a Secure Ubiquitous System,” Computer Intelligence and Security, Springer Berlin/Heidelberg, LNCS vol. 4456/2007, pp. 385-395, Sep. 2007.
  91. T. Sato, K. Kikuchi and M. Fukase, “Port-Scan Detection Unit for H-HIPS,” Proc. of CCCT, vol. II, pp. 250-255, Jul. 2007.
  92. M. Fukase and T. Sato, “Compilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor,” Proc. of WMSCI2007, vol. V, pp. 245-250, Jul. 2007.
  93. M. Fukase and T. Sato, “Exploiting Design and Testing Methods of High-Speed Power Conscious Wave-Pipelines,” Proc. of NASA2007, pp. 5.1.1-5.1.6, Jun. 2007.
  94. M. Fukase, H. Takeda and T. Sato, “Hardware Cryptography-Embedded Multimedia Mobile Processor,” Proc. of ECTI-CON 2007, vol. 2, pp.1128-1131, May 2007.
  95. T. Sato, K. Kikuchi and M. Fukase, “Verifying Various Generation of Random Number Sequence on Wave-Pipelined PRNG,” Proc. of ECTI-CON 2007, vol. 1, pp. 21-24, May 2007
  96. M. Fukase and T. Sato, “Design of a Hardware-Cryptography-Embedded Processor for Pervasive Computing,” Proc. of UCAS-3, pp. 15-22, Apr. 2007.
  97. M. Fukase, H. Takeda, R. Tenma, K. Noda, Y. Sato, R. Sato and T. Sato, “Development of a Multimedia Stream Cipher Engine,” Proc. of IEEE ISPACS 2006, pp. 562-565, Dec. 2006.
  98. T. Sato, K. Kikuchi and M. Fukase, “A PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence,” Proc. of IEEE TENCON 2006, pp. CA2.1.1-CA2.1.4, Nov. 2006.
  99. M. Fukase, H. Takeda and T. Sato, “Hardware/Software Co-Design of a Secure Ubiquitous System,” Proc. of CIS’06, pp. 1307-1310, Nov. 2006.
  100. T. Sato, K. Kikuchi and M. Fukase, “Chip Design of a Wave-Pipelined PRNG,” Proc. of ISCIT2006, pp. 978 -983, Oct. 2006.
  101. M. Fukase and T. Sato, “Innovative Ubiquitous Cryptography and Sophisticated Implementation,” Proc. of ISCIT2006, pp. 364 -369, Oct. 2006.
  102. M. Fukase, R. Akaoka and T. Sato, “Hardware Cryptography-Embedded Multimedia Mobile System,” Proc. of WMSCI2006, vol. III, pp. 225-230, Jul. 2006.
  103. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “Waved-LFSR Circuit for Hardware-based Intrusion Detection System,” Proc. of ECTI-CON2006, vol. I, pp. 30-33, May 2006.
  104. M. Fukase, R, Akaoka, L. Lei, C. T. Shu and T. Sato, “Hardware Cryptography for Ubiquitous Computing,” Proc. of ISCIT2005, vol. 1, pp. 462-465, Oct. 2005.
  105. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “Waved-PRNG for a Wave-Pipelining Test Circuit,” Proc. of 12th NASA Symposium on VLSI, pp. 3.3.1-3.3.4, Oct. 2005.
  106. M. Fukase, R. Akaoka and T. Sato, “Hardware Cryptography-Embedded Multimedia Mobile Processor for Ubiquitous Computing,” Proc. of 12th NASA Symposium on VLSI, pp. 1.2.1-1.2.6, Oct. 2005.
  107. T. Sato, M. Fukase, Development of a Hardware-Based Solution to Unauthorized Access and Computer-Virus Problems on a Campus Wireless LAN, Journal for Academic Computing and Networking, no. 9, pp. 15-26, Sep. 2005.
  108. M. Fukase and T. Sato, “Low Energy Digital Electronics for Multimedia Ubiquitous Environments,” Proc. of EIC’05, pp, 409-414, Jul. 2005.
  109. T. Sato, D. Miyamori, R. Sakuma and M. Fukase, “Power-Consumption Aware Intrusion Detection Logic for WLAN,” Proc. of WMSCI2005, vol. III, pp. 409-414, Jul. 2005.
  110. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “Hardware Security-Embedded Wireless LAN Processor,” Proc. of ECTI-CON2005, vol. II, pp. 839-842, May 2005.
  111. Y. Sato, T. Sato, M. Fukase, Development of a Multimedia Mobile Processor with Embedded Hardware Security and Simultaneous Thread-Level Processing, Social Information, vol.14, no. 2, pp. 97-107, Mar. 2005.
  112. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “Performance Analysis of Wave-Pipelined LFSR,” Proc. of ISCIT 2004, pp. 694-699, Oct. 2004.
  113. M. Fukase and T. Sato, “A Graphic Approach for Wave-Pipelines Design,” Proc. of ISCIT 2004, pp. 688-693, Oct. 2004.
  114. M. Fukase, Y. Nakamura, R. Akaoka and T. Sato, “Development of a Multimedia Mobile Processor,” Proc. of ISCIT 2004, pp. 672-677, Oct. 2004.
  115. M. Fukase, Y. Sato and T. Sato, “Design of a Hardware Security-Embedded Multimedia Mobile Processor,” Proc. of ISCIT 2004, pp. 362-367, Oct. 2004.
  116. R. Egawa, M. Fukase, T. Sato and T. Nakamura, “Could Wave Pipeline Overcome Commodity Pipelines?,” Information, vol. 7, no. 5, pp. 631-640, Sep. 2004.
  117. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “High-Speed and Low-Power LFSR by Wave-Pipelining,” Proc. of CCCT, vol. III, pp. 396-401, Aug. 2004.
  118. T. Sato, D. Miyamori, R. Sakuma and M. Fukase, “Unauthorized Port Access Detection in the H-HIDS,” Proc. of 8th SCI2004, pp. 389-394, Jul. 2004.
  119. M. Fukase, A. Fukase, Y. Sato and T. Sato, “Cryptographic System by a Random Addressing-Accelerated Multimedia Mobile Processor,” Proc. of 8th SCI2004, vol. II, pp. 174-179, Jul. 2004.
  120. M. Fukase, A. Fukase, Y. Sato and T. Sato, “Exploiting a Hardware Security-Embedded Multimedia Mobile Processor System and its Application,” Proc. of ITC-CSCC2004, pp. 7C3L-3-1-7C3L-3-4, Jul. 2004.
  121. T. Sato, R. Egawa, M. Fukase, T. Nakamura, Development of an Evaluation Test Circuit for High-Speed, Low-Power Wave Pipelines, Social Information, vol.13, no. 2, pp. 99-108, Mar. 2004.
  122. T. Sato and M. Fukase, “Reconfigurable Hardware Implementation of Host-Based IDS,” Proc. of the 9th Asia-Pacific Conference on Communication, vol. 2, pp. 849-853, Sep. 2003.
  123. M. Fukase and T. Sato, “Power Conscious Endeavor in Processors to Speed Up Random Sampling,” Proc. of 7th SCI2003, vol. V, pp111-116, Jul. 2003.
  124. R. Egawa, M. Fukase, T. Sato and T. Nakamura, “Designing a 32-bit Wave-pipelined ALU,” Proc. of 5th ICCIT, pp. 490-494, Dec. 2002.
  125. M. Fukase, T. Sato, R. Egawa and T. Nakamura, “A Wave-Pipelined Biprocessor Achieving Remarkable Compatibility between Low Power and High Speed, Proc. of 10th NASA Symposium on VLSI Design, pp. 8.3.1-8.3.8, Mar. 2002.
  126. M. Fukase, T. Sato, R. Egawa and T. Nakamura, “Designing a Wave-Pipelined Vector Processor,” Proc. of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies, pp. 351-356, Oct. 2001.
  127. M. Fukase, T. Sato, R. Egawa and T. Nakamura, “Scaling up of Wave-Pipelines,” Proc. of the Fourteenth International Conference on VLSI Design, pp. 439-445, Jan. 2001. Multifunctional Wave-Pipelines,” Proc. of 9th NASA Symposium on VLSI Design, pp.6.3.1-6.3.17, Nov. 2000.
  128. M. Fukase, T. Sato, R. Egawa and T. Nakamura, “Breakthrough of Suparscalar Processors by Multifunctional Wave-Pipelines,” Proc. of 9th NASA Symposium on VLSI Design, pp.6.3.1-6.3.17, Nov. 2000.
  129. T. Sato, E. Rashid, K. Hamada, M. Fukase and T. Nakamura, “Performance Analysis of the Wireless Hypermedia System,” Proc. of lCPWC'97, pp. 293-296, Dec. 1997.
  130. E. Rashid, T. Sato, K. Hamada, M. Fukase and T. Nakamura, “An Addressing System Protocol for Wireless Hypermedia,” Proc. of Fifth Symposium on Communications and Vehicular Technology, pp. 13-17, Oct. 1997.
  131. M. Ohtsuka, T. Sato, E. Rashid, M. Fukase and T. Nakamura, “Digital Broadcasting for Multimedia System,” Proc. of International Wireless and Telecommunications Symposium / Exhibition, vol. 3, pp. l07-110, May 1997.

Non-Peer-Reviewed Publications

  1. T. Sato, “Technical Development of Intrusion Prevention Systems with Reconfigurable Devices,” IEICE Technical Report SIS2023-19, vol. 123, no. SIS-208, pp. 19-24, Oct. 2023. (Invited)
  2. M. Toyoshima and T. Sato, “Development of a CAD Tool for FPGA Circuits That Can Be Designed with RTL,” Proc. of the 85th National Convention of the Information Processing Society of Japan, vol. 1, pp. 3-4, Feb. 2023.
  3. T. Sato, K. Sudo, H. Ogura, Y. Takeuchi, M. Kasai, “Establishing an Operational Framework for a Next-Generation Firewall Using a MAC Address Authentication System,” Proceedings of the 20th Annual Conference on Academic Computing and Networking, pp. 14-17, Sep. 2016,
  4. N. Mimura, T. Takaki, K. Narita, K. Ichinohe, A. Kurokawa, T. Sato, M. Fukase, “Optimal Design of a Ubiquitous Processor Chip,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1777-17789, Sep. 2012.
  5. K. Narita, N. Mimura, T. Takaki, K. Ichinohe, M. Fukase, T. Sato, “Integration of Clocking Schemes in a Ubiquitous Processor,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1775-1776, Sep. 2012.
  6. K. Sudo, H. Ogura, T. Sato, “Construction of an On-Campus IP Telephony Network Using the Campus LAN,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1151-1152, Sep. 2012.
  7. T. Sato, Y. Takeuchi, H. Ogura, K. Sudo, T. Akahira, Y. Fukuma, N. Hasegawa, M. Fukase, “A Campus Paperless Meeting and Information-Sharing System Using Tablet Computers,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1149-1150, Sep. 2012.
  8. K. Ichinohe, K. Narita, N. Mimura, T. Takaki, A. Kurokawa, T. Sato, M. Fukase, “Trade-Off Design of a Ubiquitous Processor,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1115-1120, Sep. 2012.
  9. T. Sato, T. Kataoka, M. Fukase, “Development of a Multiplexed Bus for IPS Processors,” Proceedings of the 2012 IEEJ Electronics, Information and Systems Division Conference, pp. 1133-1136, Sep. 2012.
  10. T. Sato, T. Imada, P. Moungnoul, M. Fukase, “Hardware Implementation of an Improved WEP Algorithm,” IEICE Technical Report, Vol. 112 No. 78, pp. 1-5, Jun. 2012.
  11. H. Uchiumi, T. Ishihara, N. Mimura, T. Takaki, K. Narita, M. Fukase, T. Sato, “Development of a Ubiquitous Processor Chip,” Information Processing Society of Japan, FIT2011, vol. 1, pp. 433-438, Sep. 2011.
  12. K. Narita, H. Uchiumi, T. Ishihara, N. Mimura, T. Takaki, M. Fukase, T. Sato, “Optimal Design of a Ubiquitous Processor,” Information Processing Society of Japan, FIT2011, vol. 1, pp. 427-432, Sep. 2011.
  13. T. Imada, T. Sato, M. Fukase, “Development of a High-Security WEP Processor,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 90, Aug. 2011.
  14. K. Ichinohe, K. Narita, N. Mimura, T. Takaki, H. Uchiumi, M. Fukase, T. Sato, “Evaluation of a Ubiquitous Processor Implementing Gated Clocks,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 104, Aug. 2011.
  15. Y. Sasaki, T. Kataoka, T. Sato, M. Fukase, “Development of a CPU for Network Processors,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 106, Aug. 2011.
  16. T. Kataoka, Y. Sasaki, T. Sato, M. Fukase, “Development of a Multiplexed Bus Using Wave Pipelining,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 102, Aug. 2011.
  17. N. Mimura, H. Uchiumi, T. Ishihara, K. Narita, T. Takaki, M. Fukase and T. Sato, “Evaluation of a Double Cipher-Implemented Ubiquitous Processor,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 110, Aug. 2011.
  18. T. Takaki, H. Uchiumi, T. Ishihara, M. Fukase, A. Kurokawa, T. Sato, “Optimal Design of a Wave-Pipelined MFU,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 105, Aug. 2011.
  19. T. Ishihara, H. Uchiumi, M. Fukase, T. Sato, “Development and Evaluation of a Stream-Cipher Engine Chip,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 111, Aug. 2011.
  20. H. Uchiumi, T. Ishihara, N. Mimura, T. Takaki, K. Narita, M. Fukase, T. Sato, “Design of a Next-Generation Ubiquitous Processor Chip,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 103, Aug. 2011.
  21. R. Noku, M. Fukase, T. Sato, “A Study on Wave-Pipelining Sequential Circuits,” Proceedings of the 2011 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, pp. 116, Aug. 2011.
  22. H. Uchiumi, T. Ishihara, N. Mimura, T. Takaki, K. Narita, M. Fukase, T. Sato, “Development of a Ubiquitous Processor Chip,” IEICE Technical Report, vol. 111, no. 176, pp. 79-84, Aug. 2011.
  23. H. Uchiumi, T. Ishihara, N. Mimura, K. Narita, T. Takaki, M. Fukase, T. Sato, “Chip Development of a Ubiquitous Processor,” IEICE Technical Report, vol. 110, no. 344, pp. 43-48, Dec. 2010.
  24. T. Takaki, H. Uchiumi, T. Ishihara, K. Tsai, M. Fukase, T. Sato, “Evaluation of Fundamental Design Parameters for a Wave-Pipelined MFU,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 147, Aug. 2010.
  25. T. Ishihara, H. Uchiumi, M. Fukase, T. Sato, “Development of a Stream-Cipher Engine Chip,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 208, Aug. 2010.
  26. N. Mimura, H. Uchiumi, T. Ishihara, M. Fukase, T. Sato, “Evaluation of a Ubiquitous Processor,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 146, Aug. 2010.
  27. K. Narita, K. Tsai, T. Ishihara, H. Uchiumi, M. Fukase, T. Sato, “Processor Architecture Integrating Multiple Clocking Schemes,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 148, Aug. 2010.
  28. H. Uchiumi, T. Ishihara, M. Fukase, T. Sato, “Development and Evaluation of a Next-Generation Ubiquitous Processor Chip,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 282, Aug. 2010.
  29. M. Kon, K. Saito, T. Sato, M. Fukase, “Power Evaluation of a Wave-Pipelined Firewall Unit,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 142, Aug. 2010.
  30. K. Saito, T. Sato, M. Fukase, “Development of a Packet Filtering Unit,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 141, Aug. 2010.
  31. Y. Ohsumi, M. Fukase, T. Sato, “Measurement of a Prototype Stream-Cipher Engine Chip,” Proceedings of the 2010 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 281, Aug. 2010.
  32. S. Imaruoka, T. Sato, M. Fukase, “Development of a Wired-Logic Network Interface,” Proceedings of the 2010 IEICE General Conference, ISS Special Student Poster Session, ISS-P-142, p. 42, Mar. 2010.
  33. T. Ishihara, H. Uchiumi, Y. Ohsumi, M. Fukase, T. Sato, “Development of a Stream-Cipher Engine Chip,” IEICE Technical Report, vol. 109, pp. 336, pp. 95-100, Dec. 2009.
  34. Y. Ohsumi, A. Yokoyama, M. Fukase, T. Sato, “Development of a Parallelizing Compiler for a Ubiquitous Processor,” Information Processing Society of Japan　FIT2009, vol. 1, pp. 427-428, Sep. 2009.
  35. A. Yokoyama, Y. Ohsumi, M. Fukase, T. Sato, “Dependence of MFU Performance on the Number of Wave Stages,” Information Processing Society of Japan　FIT2009, vol. 1, pp. 447-448, Sep. 2009.
  36. K. Saito, S. Imaruoka, T. Sato, M. Fukase, “Evaluation of a Packet Filtering Unit,” Information Processing Society of Japan　FIT2009, vol. 4, pp. 129-130, Sep. 2009.
  37. S. Imaruoka, T. Sato, M. Fukase, “Detection of Share Traffic Using SHA-1 and RC6 Decryption Units,” Information Processing Society of Japan　FIT2009, vol. 4, pp. 123-124, Sep. 2009.
  38. Y. Ohsumi, A. Yokoyama, M. Fukase, T. Sato, “Optimal Design of a Stream-Cipher Engine,” Information Processing Society of Japan　FIT2009, vol. 1, pp. 443-444, Sep. 2009.
  39. T. Ishihara, H. Uchiumi, Y. Ohsumi, M. Fukase, T. Sato, “Development of a Stream-Cipher Engine Chip,” IEICE Technical Report, vol. 109, no. 171, pp. 83-88, Aug. 2009.
  40. K. Saito, K. Ito, S. Imaruoka, T. Sato, M. Fukase, “FPGA Implementation of a Wave-Pipelined Firewall Unit,” IEICE Technical Report, vol. 109, no. 171, pp. 83-88, pp. 77-81, Aug. 2009.
  41. H. Uchiumi, T. Ishihara, Y. Okuma, M. Fukase, T. Sato, “Improved Wave-Pipelining of a Ubiquitous Processor,” Proceedings of the 2009 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 109, Aug. 2009.
  42. K. Ito, K. Saito, S. Imaruoka, T. Sato, M. Fukase, “Evaluation of a Wave-Pipelined Firewall Unit,” Proceedings of the 2009 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 111, Aug. 2009.
  43. T. Ishihara, H. Uchiumi, Y. Ohsumi, M. Fukase, T. Sato, “Improvement of a Stream-Cipher Engine,” Proceedings of the 2009 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 110, Aug. 2009.
  44. M. Fukase, A. Yokoyama, Y. Okuma, R. Murakami, T. Sato, “Design Techniques for a Ubiquitous Processor Chip,” Proceedings of the Academic Plaza Program, pp. 17-23, Jun. 2009.
  45. A. Yokoyama, K. Noda, M. Fukase and T. Sato, “A Waved MFU for a Ubiquitous Processor,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 38, Aug. 2008.
  46. R. Murakami, A. Yokoyama, M. Fukase, T. Sato, “A Parallelizing Compiler for a Load-Balanced Next-Generation Ubiquitous System,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 224, Aug. 2008.
  47. Y. Ohsumi, K. Noda, M. Fukase, T. Sato, “Performance Evaluation of a Stream-Cipher Engine,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 199, Aug. 2008.
  48. S. Imaruoka, T. Sato, M. Fukase, “A Hardware-Based Countermeasure for File-Sharing Software,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 98, Aug. 2008.
  49. K. Saito, S. Imaruoka, T. Sato, M. Fukase, “A Study on the Practical Implementation of a Network Processor,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 100, Aug. 2008.
  50. K. Noda, A. Yokoyama, M. Fukase and T. Sato, “Exploiting Double Hardware Cryptography,” Proceedings of the 2008 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 39, Aug. 2008.
  51. K. Noda, A. Yokoyama, H. Takeda, M. Fukase, T. Sato, “Enhancement of Multimedia Functions Through Multifunctional Wave-Pipelining of the Execution Stage,” IEICE Technical Report, vol. 107, no. 508, pp. 7-12, Mar. 2008.
  52. H. Takeda, K. Noda, M. Fukase, T. Sato, “Improvement of the HCgorilla Ubiquitous Processor,” IEICE Technical Report, vol. 107, no. 508, pp. 31-36, Mar. 2008.
  53. K. Kikuchi, T. Sato, M. Fukase, “Hardware Implementation of an Intrusion Prevention System,” IPSJ SIG Technical Report 2007-CSEC, no. 39, pp. 13-18, Dec. 2007.
  54. Y. Iwamoto, R. Tenma, H. Takeda, K. Noda, M. Fukase, T. Sato, “A Multimedia Stream-Cipher Engine,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 194, Aug. 2007.
  55. A. Yokoyama, H. Takeda, K. Noda, M. Fukase, T. Sato, “A Study on Hardware/Software Co-Design of HCgorilla,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 189, Aug. 2007.
  56. K. Noda, H. Takeda, M. Fukase and T. Sato, “Multimedia Performance of a Ubiquitous Processor,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 16, Aug. 2007.
  57. H. Takeda, K. Noda, M. Fukase, T. Sato, “A Study on Scaling Up HCgorilla,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 188, Aug. 2007.
  58. S. Imaruoka, K. Narita, K. Kikuchi, T. Sato, M. Fukase, “Practical Implementation of a Winny Defense Unit,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 107, Aug. 2007.
  59. K. Kikuchi, T. Sato, M. Fukase, “Development of a Hardware-Based Intrusion Prevention System,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 106, Aug. 2007.
  60. C. Ito, M. Fukase, T. Sato, “Development of a Parallelizing Compiler for the HCgorilla Ubiquitous Processor,” Proceedings of the 2007 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 98, Aug. 2007.
  61. K. Noda, H. Takeda, M. Fukase, T. Sato, “Enhancement of HCgorilla Multimedia Functions,” IPSJ SIG Technical Report, vol. 2007, no. 58, pp.85-90, Jun. 2007.
  62. M. Fukase and T. Sato, “Design Techniques of Wave Pipelines,” IEICE Technical Report, ICD2007, vol. 28, pp. 67-72, May 2007.
  63. K. Kikuchi, T. Sato, M. Fukase, “Operational Verification of a Wave-Pipelined PRNG Circuit,” 2006 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 208, Aug. 2006.
  64. Y. Sato, L. Liu, M. Fukase, T. Sato, “Hardware Cryptography Using HCgorilla,” Proceedings of the 2006 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 209, Aug. 2006.
  65. R. Sato, M. Fukase, T. Sato, “Development of a Parallelizing Compiler for the HCgorilla Ubiquitous Processor,” Proceedings of the 2006 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 265, Aug. 2006.
  66. Y. Watanabe, M. Fukase, T. Sato, “Development of a Java Interface for the HCgorilla Ubiquitous Processor,” Proceedings of the 2006 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 266, Aug. 2006.
  67. H. Takeda, K. Noda, R. Tenma, M. Fukase, T. Sato, “Development of a Multimedia Stream-Cipher Engine,” Proceedings of the 2006 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, p. 207, Aug. 2006.
  68. R. Sakuma, D. Miyamori, M. Fukase and T. Sato, “Development of a Security-Enforced Network Interface Card for Wireless LAN,” Proceedings of the 2005 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, Aug. 2005.
  69. R. Akaoka, M. Fukase and T. Sato, “Hardware Cryptography-Embedded Multimedia Mobile Processor,” Proceedings of the 2005 Joint Convention of Electrical and Information Engineering Societies in the Tohoku Region, Aug. 2005.
  70. M. Fukase, Y. Sato, Y. Nakamura, R. Akaoka and T. Sato, “Hardware Cryptography-Embedded Multimedia Mobile Processor,” IEICE Technical Report, vol. 104, no. 735, pp. 31-36, Mar. 2005.
  71. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, “Securely Aware Design of a Power Conscious High-Speed Wireless LAN System,” IEICE Technical Report, vol. 104, no. 735, pp.11-16, Mar. 2005.
  72. D. Miyamori, R. Sakuma, T. Sato, M. Fukase, “Evaluation of a Wave-Pipelined CRC Circuit,” Proceedings of the 2003 Joint Convention of Electrical and Information Engineering Societies in Hokkaido, Oct. 2003.
  73. K. Mikuni, Y. Nakamura, R. Imai, M. Fukase, T. Sato, “Implementation of a Multimedia Processor for Mobile Computing,” Information Processing Society of Japan, Proceedings of FIT2003, Sep. 2003.
  74. A. Fukase, Y. Sato, T. Sato, M. Fukase, T. Araki, “A Cryptographic System Using a Multimedia Processor with Enhanced Random Addressing,” Information Processing Society of Japan, Proceedings of FIT2003, Sep. 2003.
  75. T. Sato, M. Fukase, T. Nakamura, “Performance Evaluation of a Wave-Pipelined ALU,” IEICE Technical Report, CPSY, vol. 100, no. 20, pp. 1-6, Apr. 2000.
  76. T. Kano, T. Sato, Y. Nagashima, T. Nagase, M. Fukase, T. Nakamura, “A Switch Architecture for Point-to-Multipoint Communication in ATM Networks,” Workshop on Multimedia Communication and Distributed Processing, pp. 95-98, Oct. 1996

Doctoral Dissertation

T. Sato, “Architecting and Designing Wave-Pipelined Microprocessors,” Ph.D. dissertation, Graduate School of Engineering, Tohoku University, 2001.

Contact

2-3-1 Oyachi Nishi, Atsubetsu-ku, Sapporo
004-8631, Japan
Department of Management and Information Science, School of Economics, Hokusei Gakuen University　
Tomoaki Sato　
E-mail: t-sato@hokusei.ac.jp