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  1. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gA Circuit Design for IEEE 802.11ac by ASIC-FPGA Co-Design,h Proc. of ISMAC 2017, pp. 89-92, Aug. 2017.
  2. P. Moungnoul and T. Sato, gInvestigated of DOCSIS Mesurement Results for Performance Improvement,h Proc. of ISMAC 2017, pp. 195-198, Aug. 2017.
  3. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gRCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined Operation,h ECTI Transactions CIT, vol. 11, no. 1, pp. 11-20, May 2017.
  4. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gThroughput of a Firewall Unit on FPGAs developed by the RTL Design Methodology,h Proc. of iEECON 2017, vol. 2, pp. 423-426, Mar. 2017.
  5. K. Ogiwara, K. Higuchi, T. Sato, S. Premrudeepreechacharn and K. Jirasereeamornkul, "Approximate 2-Degree-of-Freedom Digital Control of an Interleaved Low Voltage DC-DC Buck Converter," Proc. of iEECON 2017, vol. 1, 13-16, Mar. 2017.
  6. S. ChivapreechaCN. Ronnaronglit and T. Sato, gChaos in Digital Filter for Digital Image Encryption,h Proc. of IWAIT2017, pp. 6C.5.1-6C.5.4, Jan. 2017.
  7. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gAn FPGA Architecture for ASIC-FPGA Co-Design to Streamline Processing of IDSs,h Proc. of CTS 2016, pp. 412-417, Oct. 2016.
  8. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gDesigning a Firewall Unit on the FPGA Composed of Selectors,h Proc. of SISA 21016, pp. 53-58, Sept. 2016.
  9. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi, gProposal of an Automatic Running AP in Wireless LANs for the Maximization of the Throughput,h Proc. of CreTech 2016, pp. 9-11, Aug. 2016.
  10. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gRCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined OperationCProc. of ECTI-CON 2016, pp. 1251.1-1251.6, Jun. 2016.
  11. K. Hanabusa, K. Higuchi, T. Sato and K. Jirasereeamornkul, gApproximate 2-Dgree-of-Freedom Control of a Class-D Amplifier Using FPGA,h Proc. of ECTI-CON 2016, pp. 1152.1-1152.6, Jun. 2016.
  12. T. Sato, S. Chivapreecha and P. Moungnoul, gA Connection Block Implemented in the RTL Design for Delay Time Equalization of Wave-Pipelining,h Journal of Systemics, Cybernetics and Informatics, vol. 14, no. 1, pp. 49-54, Apr. 2016.
  13. N. Ronnaronglit, S. Chivapreecha and T.Sato, gAn Improved Digital Image Encryption Using Chaos in Digital Filter,h Proc. of ISMAC 2015, pp. 297-301, Sept. 2015.
  14. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi, gOptimization of Radio Waves of Wi-Fi LANS for Universities,h Proc. of CreTech 2015, p. 22, Aug. 2015,
  15. T. Sato, S. Chivapreecha and P. Moungnoul, gFine-Tuning of Wave-Pipelines on FPGAs Developed by the RTL Design,h Proc. of ECTI-CON 21015, pp. 1230.1-1230.6, Jun. 2015.
  16. T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi gProposal of the security log collection method of public Wi-Fi services on private IPv4 address spaces utilizing Raspberry Pi,h Proc. of ICESIT 2015, pp. 6-7, Jun. 2015.
  17. T. Sato, S. Chivapreecha and P. Moungnoul, gThe Potential of Routes Configured with the Switch Matrix by RTL,h Applied Mechanics and Materials Journal, vol. 781, pp. 189-192, May 2015.
  18. T. Sato, S. Chivapreecha and P. Moungnoul, gWiring Control by RTL Design for Reconfigurable Wave-Pipelined Circuits,h Proc. of APSIPA ASC 2014, pp. WP1-3-1-WP1-3-6, Dec. 2014.
  19. T. Sato, S. Chivapreecha and P. Moungnoul, gDesign and Analysis of Crossbar Switch Circuits for Reconfigurable Wave-Pipelined Circuits,h Proc. of CreTech 2014, pp. 12-15, Aug. 2014.
  20. T. Sato, S. Chivapreecha and P. Moungnoul, gEvaluation of Logic Blocks for Reconfigurable Wave-Pipelined Circuits with 45nm CMOS Technology,h Proc. of ITC-CSCC2014, pp. 464-465, Jul. 2014.
  21. T. Sato, S. Chivapreecha and P. Moungnou, gA Crossbar Switch Circuit Design for Reconfigurable Wave-Pipelined Circuits,h Proc. of WMSCI 2014, vol. II, pp. 200-205, Jul. 2014.
  22. T. Sato, P. Moungnoul, S. Chivapreecha and K. Higuchi, gPerformance Estimates of an Embedded CPU for High-Speed Packet Processing,h Proc. of ECTI-CON 2014, pp.1298.1-1298-5, May 2014.
  23. T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi, gEvaluations of Waved-Shift Registers for Multiplexed Bus,h Proc. of iEECON2014, pp. 109.1-109.4, Mar. 2014.
  24. Y. Adachi, K. Higuchi, T. Sato and K. Chamnongthai, gRobust Digital Control for Interleaved PFC Boost Converters Using an Approximate 2DOF Current Controller,h ECTI Transactions EEC, vol. 12, no. 1, pp. 37-43, Feb. 2014.
  25. T. Sato, S. Chivapreecha and P. Moungnoul, gA Logic Block for Wave-Pipelining,h Proc. of IMETI 2013, pp. 130-134, Jul. 2013.
  26. T. Sato and P. Moungnoul, gHardware Amount Evaluation of the Improved WEP on an FPGA,h Proc. of ECTI-CON 2013, pp. 1760.1-1760.6, May 2013.
  27. Y. Adachi, Y. Fukaishi, K. Higuchi, T. Sato and K. Chamnongthai, gRobust Digital Control for Interleave PFC Boost Converter,h Proc. of The 18th International Symposium on ARTIFICIAL LIFE AND ROBOTICS, p. 185, Feb. 2013.
  28. Y. Adachi, K. Higuchi, T. Kajikawa, T. Sato and K. Chamnongthai, gDigital PI control for interleave PFC boost converter,h Proc. of The 18th International Symposium on ARTIFICIAL LIFE AND ROBOTICS, p. 163, Feb. 2013.
  29. M. Fukase, K. Ichinohe, K. Narita, T. Takaki, N. Mimura, T. Sato and A. Kurokawa, gDevelopment of a Next Generation Ubiquitous Processor Chip,h ECTI Transactions CIT, vol. 6, no. 2, pp. 120-127, Nov. 2012.
  30. T. Sato, P. Moungnoul and M. Fukase, gDelay Time Analysis of Reconfigurable Firewall Unit,h Journal of Systemics, Cybernetics and Informatics, vol. 10, no. 5, pp. 80-84, Oct. 2012.
  31. T. Sato, P. Moungnoul and M. Fukase, gPacket Filtering Circuits for Smart Phones,h Proc. of The 16th World Multi-Conference on Systemics, Cybernetics and Informatics, vol. II, pp. 5-9, Jul. 2012.
  32. M. Fukase, K. Ichinohe, N. Mimura, K. Narita, T. Takaki and T. Sato, gVLSI Implementation With Double Cipher and Media Processing for Ad-Hoc Network,h Proc. of ECTI-CON 2012, pp. 1162-1-1162-4, May 2012.
  33. M. Fukase and T. Sato, gDouble Cipher Implementation in a Ubiquitous Processor Chip,h American Journal of Computer Architecture, vol.1 no.1 pp. 6-11, May 2012.
  34. T. Sato, P. Moungnoul and M. Fukase, gThroughput Evaluation of Improved WEP Processing on a Mobile Processor,h Proc. of 1st International Symposium on Technology for Sustainability, pp. 325-328, Jan. 2012.
  35. M. Fukase, H. Uchiumi, K. Narita, T. Takaki, N. Mimura, K. Ichinohe, T. Sato and A. Kurokawa, gDevelopment of a Next Generation Ubiquitous Processor Chip,h Proc. of the 18th IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 225.1-225.4, Dec. 2011.
  36. M. Fukase, N. Mimura, K. Narita, T. Takaki, H. Uchiumi, T. Ishihara and T. Sato, gEvaluation for the Power Conscious Optimum Design of a Ubiquitous Processor,h Proc. of the 4th International Multi-Conference on Engineering and Technological Innovation, vol. II, pp. 104-108, Jul. 2011.
  37. M. Fukase, H. Uchiumi, T. Ishihara, N. Mimura, K. Narita, T. Takaki and T. Sato, gDouble Cipher Implementation in a Ubiquitous Processor Chip,h Proc. of ECTI-CON 2011, pp.125-128, May 2011.
  38. T. Sato, P. Moungnoul and M. Fukase, gCompatible WEP Algorithm for Improved Cipher Strength and High-Speed Processing,h Proc. of ECTI-CON 2011, pp. 401-404, May 2011.
  39. M. Fukase, T. Ishihara, H. Uchium and T. Sato, gDesign and Evaluation of a Waved MFU,h Proc. of APSIPA ASC 2010, p. 70, Dec. 2010.
  40. M. Fukase, H. Uchiumi, T. Ishihara and T. Sato, gImpact of Using a Double Cipher Scheme on the Implementation of a Particular Ubiquitous Processor,h Proc. of ISCIT 2010, pp. 821-826, Oct. 2010.
  41. M. Fukase and T. Sato, gA Ubiquitous Processor Built-in a Waved Multifunctional Unit,h ECTI Transactions CIT, vol. 4, no. 1, pp. 1-7, May 2010.
  42. T. Sato, K. Ito, K. Saito, P. Moungnoul and M. Fukase, gDevelopment of a shift register for Firewall Circuits by Wave-Pipelined Operations,h Proc. of ICT2010, pp. w4c-1-1-w4c-1-4, Aug. 2010.
  43. T. Sato, P. Moungnoul and M. Fukase, gPower Control Scheme for H-HIPS in Mobile Communications,h Proc. of ICT2010, pp. s3-3-1-s3-3-4, Aug. 2010.
  44. P. Moungnoul, A. Sopin and T. Sato, gPerformance of IR-UWB PSM and BPM over S-V Channel Model,h Proc. of ICT2010, pp. W2A-1-1-W2A-1-4, Aug. 2010.
  45. M. Fukase and T. Sato, gH/S Collaborative Development of a Ubiquitous Processor Free from Instruction Scheduling and Pipeline Disturbance,h Proc. of 9the IEEE/ACIS International Conference on Computer and Information Science, pp. 57-62, Aug. 2010.
  46. T. Sato, P. Moungnoul, K. Saito and M. Fukase, gDevelopment of a WiMAX Processor by Using a CPLD,h Proc. of IMETI2010, vol. II, pp. 128-133, Jun. 2010.
  47. M. Fukase, A. Yokoyama, T. Ishihara, H. Uchiumi and T. Sato, gWave Degree versus Dominant Characteristics of a Waved Multifunctional Unit,h Proc. of IMETI2010, vol. II, pp. 164-168, Jun. 2010.
  48. P. Moungnoul N. Worawatjirakul S. Junnapiya U. Thongrak J. Chanwutitum and T. Sato, gTCP Performance Improvement for Wireless Access using Cross-Layer MIMO Adaptive Modulation,h Proc. of ICESIT2010, pp. 104.1-104.6, Feb. 2010.
  49. P. Moungnoul, J. Jarassriwilai, U. Thongrak, N. Panitjaroen and T. Sato, gMIMO Adaptive Modulation with Cross-Layer Model of Queuing over Nakagami Fading,h Proc. of ICESIT2010, pp. 92.1-92.6, Feb. 2010.
  50. N. Panitjaroen, P. Moungnoul, T. On-In, J. Chanwutitum and T. Sato, gPerformance Improvement of Satellite Channel with Combine Ionosphere Scintillation and Small Scale Fading using Adaptive Modulation,h Proc. of ICESIT2010, pp. 90.1-90.4, Feb. 2010.
  51. T. Sato, P. Moungnoul, k. Saito and M. Fukase, gWave-Pipelined CRC Circuits for Wireless Broadband Systems Based on W-CDMA,h Proc. of ICESIT2010, pp. 100.1-100.4, Feb. 2010.
  52. M. Fukase and T. Sato, gExploring the Optimum Buffer Size of an Emerging Stream Cipher Engine,h ECTI Transactions EEC, vol. 8, no. 1, pp. 53-58, Feb. 2010.
  53. M. Fukase, R. Murakami and T. Sato, gDesign and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor,h Proc. of ASP-DAC 2010, pp.375-376, Jan. 2010.
  54. T. Sato, S. Imaruoka and M. Fukase, gVerifying Firewall Circuits by Wave-Pipelined Operations,h Proc. of IEEE TENCON 2009, pp. WED3.P.14.1 -WED3.P.14.6, Nov. 2009.
  55. M. Fukase and T. Sato, gPerformance Evaluation of an Emerging Stream Cipher Engine,h Proc. of APSIPA ASC 2009, pp. 583-588, Oct. 2009.
  56. M. Fukase, H. Uchiumi, T. Ishihara, Y. Osumi and T. Sato, gCipher and Media Possibility of a Ubiquitous Processor,h Proc. of ISCIT 2009, pp. 343-347, Sep. 2009.
  57. M. Fukase and T. Sato, gA Waved Multifunctional Unit on Account of Multimedia Mobile Computing,h Proc. of WMSCI 2009, vol. III, pp. 86-91, Jul. 2009.
  58. T. Sato, S. Imaruoka and M. Fukase, gHardware-Based IPS for Embedded Systems,h Proc. of WMSCI 2009, vol. III, pp. 74-79, Jul. 2009.
  59. M. Fukase, A. Yokoyama and T. Sato, gA Ubiquitous Processor Embedded with Progressive Cipher Pipelines,h Proc. of GLSVLSIf09, pp. 381-384, May 2009.
  60. M. Fukase, Y. Ohsumi and T. Sato, gExploring the Optimum Buffer Size of an Emerging Stream Cipher Engine,h Proc. of ECTI-CON 2009, pp. 607-610, May 2009.
  61. T. Sato, S. Imaruoka and M. Fukase, gSystem-Level Control for Low-Power Consumption on Winny Detection System.h Proc. of ICESIT2009, pp. 10-14, Feb. 2009.
  62. T. Sato, S. Imaruoka and M. Fukase, gReconfigurable Firewall Unit by Wave-Pipelined Operations,h Proc. of ISPACS 2008, pp. 449-452, Feb. 2009.
  63. M. Fukase, K. Noda and T. Sato, gEmerging Hardware Cryptography and VLSI Implementation,h Proc. of ISPACS 2008, pp. 445-448, Feb. 2009.
  64. M. Fukase, K. Noda, A. Yokoyama and T. Sato, gDesign and Chip Implementation of the Ubiquitous Processor HCgorilla,h Proc. of ASP-DAC, pp. 129-130, Jan. 2009.
  65. T. Sato, S. Imaruoka and M. Fukase, gFPGA Implementation of Winny Packets Detection for Mobile Computing,h Proc. of ISCIT2008, pp. 204-209, Oct. 2008.
  66. M. Fukase and T. Sato, gA Ubiquitous Processor Free from Instruction Scheduling,h Proc. of ISCIT2008, pp. 75-80, Oct. 2008.
  67. ²“¡—F‹ÅCˆÉŠÛ‰ªCÆC[£­H, ƒLƒƒƒ“ƒpƒXƒlƒbƒgƒ[ƒN‚É‚¨‚¯‚éWinnyŒŸ’mŽè–@‚ÌFPGAŽÀ‘•, Šwpî•ñˆ—Œ¤‹†, no. 12, pp. 68-74, 2008”N9ŒŽ.
  68. M. Fukase and T. Sato, gCompilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor,h Journal of Systemics, Cybernetics and Informatics, vol. 5, no. 6, pp. 13-21, Sep. 2008.
  69. M. Fukase and T. Sato, gCompact FPU Design and Embedding in a Ubiquitous Processor for Multimedia Performance Enhancement,h ECTI-EEC Trans. vol. 6, no. 2, pp. 79-85, Aug. 2008.
  70. T. Sato, K. Kikuchi, S. Imaruoka and M. Fukase, gDoS Attack Analysis for H-HIPS,h Proc. of IMETI 2008, vol. II, pp. 110-115, Jul. 2008.
  71. M. Fukase and T. Sato, gDevelopment of Parallelizing Compilers of a Ubiquitous Processor,h Proc. of WMSCI2008, vol. II, pp. 220-225, Jul. 2008.
  72. M. Fukase, K. Noda, A. Yokoyama and T. Sato, gEnhancing Multimedia Processing by Wave-Pipelining Integer Units and Floating Point Units in Whole,h Proc. of ECTI-CON 2008, pp. II-681-II-684, May 2008.
  73. T. Sato, K. Kikuchi, S. Imaruoka and M. Fukase, gLow-Power Scheme of Portscan Detection Unit by Using Embedded Technology,h Proc. of ICESIT2008, pp. 122-125, Feb. 2008.
  74. M. Fukase, H. Takeda, K. Noda, A. Yokoyama and T. Sato, gAd-hoc Cipher by a Ubiquitous Processor,h Proc. of ICESIT 2008, pp. 118-121, Feb. 2008.
  75. M. Fukase and T. Sato, gA Stream Cipher Engine for Ad-hoc Security,h Proc. of CISf2007, pp. 902-906, Dec. 2007.
  76. M. Fukase, K. Noda, H. Takeda and T. Sato, gMultimedia Performance of a Ubiquitous Processor,h Proc. of ISCIT2007, pp. 1464-1469, Oct. 2007.
  77. M. Fukase, H. Takeda and T. Sato, gHardware/Software Co-Design of a Secure Ubiquitous System,h Computer Intelligence and Security, Springer Berlin/Heidelberg, LNCS vol. 4456/2007, pp. 385-395, Sep. 2007.
  78. T. Sato, K. Kikuchi and M. Fukase, gPort-Scan Detection Unit for H-HIPS,h Proc. of CCCT, vol. II, pp. 250-255, Jul. 2007.
  79. M. Fukase and T. Sato, gCompilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor,h Proc. of WMSCI2007, vol. V, pp. 245-250, Jul. 2007.
  80. M. Fukase and T. Sato, gExploiting Design and Testing Methods of High-Speed Power Conscious Wave-Pipelines,h Proc. of NASA2007, pp. 5.1.1-5.1.6, Jun. 2007.
  81. M. Fukase, H. Takeda and T. Sato, gHardware Cryptography-Embedded Multimedia Mobile Processor,h Proc. of ECTI-CON 2007, vol. 2, pp.1128-1131, May 2007.
  82. T. Sato, K. Kikuchi and M. Fukase, gVerifying Various Generation of Random Number Sequence on Wave-Pipelined PRNG,h Proc. of ECTI-CON 2007, vol. 1, pp. 21-24, May 2007
  83. M. Fukase and T. Sato, gDesign of a Hardware-Cryptography-Embedded Processor for Pervasive Computing,h Proc. of UCAS-3, pp. 15-22, Apr. 2007.
  84. M. Fukase, H. Takeda, R. Tenma, K. Noda, Y. Sato, R. Sato and T. Sato, gDevelopment of a Multimedia Stream Cipher Engine,h Proc. of IEEE ISPACS 2006, pp. 562-565, Dec. 2006.
  85. T. Sato, K. Kikuchi and M. Fukase, gA PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence,h Proc. of IEEE TENCON 2006, pp. CA2.1.1-CA2.1.4, Nov. 2006.
  86. M. Fukase, H. Takeda and T. Sato, gHardware/Software Co-Design of a Secure Ubiquitous System,h Proc. of CISf06, pp. 1307-1310, Nov. 2006.
  87. T. Sato, K. Kikuchi and M. Fukase, gChip Design of a Wave-Pipelined PRNG,h Proc. of ISCIT2006, pp. 978 -983, Oct. 2006.
  88. M. Fukase and T. Sato, gInnovative Ubiquitous Cryptography and Sophisticated Implementation,h Proc. of ISCIT2006, pp. 364 -369, Oct. 2006.
  89. M. Fukase, R. Akaoka and T. Sato, gHardware Cryptography-Embedded Multimedia Mobile System,h Proc. of WMSCI2006, vol. III, pp. 225-230, Jul. 2006.
  90. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gWaved-LFSR Circuit for Hardware-based Intrusion Detection System,h Proc. of ECTI-CON2006, vol. I, pp. 30-33, May 2006.
  91. M. Fukase, R, Akaoka, L. Lei, C. T. Shu and T. Sato, gHardware Cryptography for Ubiquitous Computing,h Proc. of ISCIT2005, vol. 1, pp. 462-465, Oct. 2005.
  92. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gWaved-PRNG for a Wave-Pipelining Test Circuit,h Proc. of 12th NASA Symposium on VLSI, pp. 3.3.1-3.3.4, Oct. 2005.
  93. M. Fukase, R. Akaoka and T. Sato, gHardware Cryptography-Embedded Multimedia Mobile Processor for Ubiquitous Computing,h Proc. of 12th NASA Symposium on VLSI, pp. 1.2.1-1.2.6, Oct. 2005.
  94. ²“¡—F‹ÅC[£­H, Šw“à–³üLAN‚É‚¨‚¯‚é•s³ƒAƒNƒZƒXEƒRƒ“ƒsƒ…[ƒ^ƒEƒCƒ‹ƒX–â‘è‚̃n[ƒh“I‰ðŒˆŽè’i‚ÌŠJ”­, Šwpî•ñˆ—Œ¤‹†, no. 9, pp. 15-26, 2005”N9ŒŽ.
  95. M. Fukase and T. Sato, gLow Energy Digital Electronics for Multimedia Ubiquitous Environments,h Proc. of EICf05, pp, 409-414, Jul. 2005.
  96. T. Sato, D. Miyamori, R. Sakuma and M. Fukase, gPower-Consumption Aware Intrusion Detection Logic for WLAN,h Proc. of WMSCI2005, vol. III, pp. 409-414, Jul. 2005.
  97. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gHardware Security-Embedded Wireless LAN Processor,h Proc. of ECTI-CON2005, vol. II, pp. 839-842, May 2005.
  98. ²“¡—zˆêC²“¡—F‹ÅC[£­H, ƒn[ƒhƒEƒFƒAƒZƒLƒ…ƒŠƒeƒB‘gž‚ÝŒ^ƒXƒŒƒbƒhƒŒƒxƒ‹“¯Žžˆ—ƒ}ƒ‹ƒ`ƒƒfƒBƒAƒ‚ƒoƒCƒ‹ƒvƒƒZƒbƒT‚ÌŠJ”­, ŽÐ‰ïî•ñ, vol.14, no. 2, pp. 97-107, 2005”N3ŒŽ.
  99. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gPerformance Analysis of Wave-Pipelined LFSR,h Proc. of ISCIT 2004, pp. 694-699, Oct. 2004.
  100. M. Fukase and T. Sato, gA Graphic Approach for Wave-Pipelines Design,h Proc. of ISCIT 2004, pp. 688-693, Oct. 2004.
  101. M. Fukase, Y. Nakamura, R. Akaoka and T. Sato, gDevelopment of a Multimedia Mobile Processor,h Proc. of ISCIT 2004, pp. 672-677, Oct. 2004.
  102. M. Fukase, Y. Sato and T. Sato, gDesign of a Hardware Security-Embedded Multimedia Mobile Processor,h Proc. of ISCIT 2004, pp. 362-367, Oct. 2004.
  103. R. Egawa, M. Fukase, T. Sato and T. Nakamura, gCould Wave Pipeline Overcome Commodity Pipelines?,h Information, vol. 7, no. 5, pp. 631-640, Sep. 2004.
  104. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gHigh-Speed and Low-Power LFSR by Wave-Pipelining,h Proc. of CCCT, vol. III, pp. 396-401, Aug. 2004.
  105. T. Sato, D. Miyamori, R. Sakuma and M. Fukase, gUnauthorized Port Access Detection in the H-HIDS,h Proc. of 8th SCI2004, pp. 389-394, Jul. 2004.
  106. M. Fukase, A. Fukase, Y. Sato and T. Sato, gCryptographic System by a Random Addressing-Accelerated Multimedia Mobile Processor,h Proc. of 8th SCI2004, vol. II, pp. 174-179, Jul. 2004.
  107. M. Fukase, A. Fukase, Y. Sato and T. Sato, gExploiting a Hardware Security-Embedded Multimedia Mobile Processor System and its Application,h Proc. of ITC-CSCC2004, pp. 7C3L-3-1-7C3L-3-4, Jul. 2004.
  108. ²“¡—F‹ÅC]ì—²•ãC[£­HC’†‘ºˆÛ’j, ‚‘¬È“d—̓EƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“—p•]‰¿ƒeƒXƒg‰ñ˜H‚ÌŠJ”­, ŽÐ‰ïî•ñ, vol.13, no. 2, pp. 99-108, 2004”N3ŒŽ.
  109. T. Sato and M. Fukase, gReconfigurable Hardware Implementation of Host-Based IDS,h Proc. of the 9th Asia-Pacific Conference on Communication, vol. 2, pp. 849-853, Sep. 2003.
  110. M. Fukase and T. Sato, gPower Conscious Endeavor in Processors to Speed Up Random Sampling,h Proc. of 7th SCI2003, vol. V, pp111-116, Jul. 2003.
  111. R. Egawa, M. Fukase, T. Sato and T. Nakamura, gDesigning a 32-bit Wave-pipelined ALU,h Proc. of 5th ICCIT, pp. 490-494, Dec. 2002.
  112. M. Fukase, T. Sato, R. Egawa and T. Nakamura, gA Wave-Pipelined Biprocessor Achieving Remarkable Compatibility between Low Power and High Speed, Proc. of 10th NASA Symposium on VLSI Design, pp. 8.3.1-8.3.8, Mar. 2002.
  113. M. Fukase, T. Sato, R. Egawa and T. Nakamura, gDesigning a Wave-Pipelined Vector Processor,h Proc. of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies, pp. 351-356, Oct. 2001.
  114. M. Fukase, T. Sato, R. Egawa and T. Nakamura, gScaling up of Wave-Pipelines,h Proc. of the Fourteenth International Conference on VLSI Design, pp. 439-445, Jan. 2001. Multifunctional Wave-Pipelines,h Proc. of 9th NASA Symposium on VLSI Design, pp.6.3.1-6.3.17, Nov. 2000.
  115. M. Fukase, T. Sato, R. Egawa and T. Nakamura, gBreakthrough of Suparscalar Processors by Multifunctional Wave-Pipelines,h Proc. of 9th NASA Symposium on VLSI Design, pp.6.3.1-6.3.17, Nov. 2000.
  116. T. Sato, E. Rashid, K. Hamada, M. Fukase and T. Nakamura, gPerformance Analysis of the Wireless Hypermedia System,h Proc. of lCPWC'97, pp. 293-296, Dec. 1997.
  117. E. Rashid, T. Sato, K. Hamada, M. Fukase and T. Nakamura, gAn Addressing System Protocol for Wireless Hypermedia,h Proc. of Fifth Symposium on Communications and Vehicular Technology, pp. 13-17, Oct. 1997.
  118. M. Ohtsuka, T. Sato, E. Rashid, M. Fukase and T. Nakamura, gDigital Broadcasting for Multimedia System,h Proc. of International Wireless and Telecommunications Symposium / Exhibition, vol. 3, pp. l07-110, May 1997.

˜_•¶i¸“Ç–³‚µj

  1. ²“¡—F‹ÅC{“¡ŸOC¬‘qLŽÀC’|“ài—åCŠ‹¼^Žõ, gMACƒAƒhƒŒƒX”FØƒVƒXƒeƒ€‚ð—p‚¢‚½ŽŸ¢‘ãƒtƒ@ƒCƒAƒEƒH[ƒ‹‚̉^—p‘̐§\’z,h ‘æ‚Q‚O‰ñŠwpî•ñˆ—Œ¤‹†W‰ï”­•\˜_•¶WCpp. 14-17C2016”N09ŒŽC
  2. ŽO‘º’¼“¹C‚–Ø—³–çC¬“cˆê‹MCˆêŒËN•½C•ì“ցC²“¡—F‹ÅC[£­H, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚̍œKÝŒv,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1777-17789, 2012”N9ŒŽ.
  3. ¬“cˆê‹M, ŽO‘º’¼“¹, ‚–Ø—³–ç, ˆêŒËN•½, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚̃NƒƒbƒNƒXƒL[ƒ€—Z‡,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1775-1776, 2012”N9ŒŽ.
  4. {“¡ŸOC¬‘qLŽÀC²“¡—F‹Å, gŠw“àLAN‚ð—˜—p‚µ‚½\“àIP“d˜b–Ԃ̍\’z,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1151-1152, 2012”N9ŒŽ.
  5. ²“¡—F‹ÅC’|“ài—åC¬‘qLŽÀC{“¡ŸOCÔ•½’qŽqC•ŸáÁ‹g‹³C’·’Jì’¼¶C[£­H, gƒ^ƒuƒŒƒbƒgƒRƒ“ƒsƒ…[ƒ^‚ð—p‚¢‚½Šw“àƒy[ƒpƒŒƒX‰ï‹c‚¨‚æ‚яî•ñ‹¤—LƒVƒXƒeƒ€,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1149-1150, 2012”N9ŒŽ.
  6. ˆêŒËN•½C¬“cˆê‹MCŽO‘º’¼“¹C‚–Ø—³–çC•ì“ցC²“¡—F‹ÅC[£­H, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚̃gƒŒ[ƒhƒIƒtÝŒv,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1115-1120, 2012”N9”N.
  7. ²“¡—F‹ÅC•Ð‰ª‘ì–çC[£­H, gIPSƒvƒƒZƒbƒTŒü‚¯‘½d‰»ƒoƒX‚ÌŠJ”­,h •½¬‚Q‚S”N“d‹CŠw‰ï“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïu‰‰˜_•¶W, pp. 1133-1136, 2012”N9ŒŽ.
  8. ²“¡—F‹ÅC¡“c’q–çCƒ‚ƒ“ƒOƒmƒEƒ‹@ƒsƒVƒFƒbƒgC[£­H, g‰ü—ÇŒ^WEPƒAƒ‹ƒSƒŠƒYƒ€‚̃n[ƒhƒEƒGƒAŽÀ‘•,h MŠw‹Z•ñ, Vol. 112 No. 78, pp. 1-5, 2012”N6ŒŽ.
  9. “àŠC°M, ÎŒ´‘ñ”ü, ŽO‘º’¼“¹, ‚–Ø—³Æ, ¬“cˆê‹M, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚ÌŠJ”­,h î•ñˆ—Šw‰ï, FIT2011, vol. 1, pp. 433-438, 2011”N9ŒŽ.
  10. ¬“cˆê‹M, “àŠC°M, ÎŒ´‘ñ”ü, ŽO‘º’¼“¹, ‚–Ø—³Æ, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚̍œKÝŒv,h î•ñˆ—Šw‰ï, FIT2011, vol. 1, pp. 427-432, 2011”N9ŒŽ.
  11. ¡“c’q–ç, ²“¡—F‹Å, [£­H, g‚ƒZƒLƒ…ƒŠƒeƒBWEPƒvƒƒZƒbƒT‚ÌŠJ”­,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 90, 2011”N8ŒŽ.
  12. ˆêŒËN•½, ¬“cˆê‹M, ŽO‘º’¼“¹, ‚–Ø—³Æ, “àŠC°M, [£­H, ²“¡—F‹Å, gGated clockŽÀ‘•ƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚Ì•]‰¿,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 104, 2011”N8ŒŽ.
  13. ²X–Ø—D¬, •Ð‰ª‘ì–ç, ²“¡—F‹Å, [£­H, gƒlƒbƒgƒ[ƒNƒvƒƒZƒbƒTŒü‚¯CPU‚ÌŠJ”­,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 106, 2011”N8ŒŽ.
  14. •Ð‰ª‘ì–ç, ²X–Ø—D¬, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“•ûŽ®‚É‚æ‚鑽d‰»ƒoƒX‚ÌŠJ”­,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 102, 2011”N8ŒŽ.
  15. N. Mimura, H. Uchiumi, T. Ishihara, K. Narita, T. Takaki, M. Fukase and T. Sato, gEvaluation of a Double Cipher-Implemented Ubiquitous Processor,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 110, 2011”N8ŒŽ.
  16. ‚–Ø—³Æ, “àŠC°M, ÎŒ´‘ñ”ü, [£­H, •ì“Ö, ²“¡—F‹Å, gƒEƒF[ƒu‰»MFU‚̍œKÝŒv,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 105, 2011”N8ŒŽ.
  17. ÎŒ´‘ñ”ü, “àŠC°M, [£­H, ²“¡—F‹Å, gƒXƒgƒŠ[ƒ€ƒTƒCƒtƒ@[ƒGƒ“ƒWƒ“‚̃`ƒbƒvŠJ”­•]‰¿,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 111, 2011”N8ŒŽ.
  18. “àŠC°M, ÎŒ´‘ñ”ü, ŽO‘º’¼“¹, ‚–Ø—³Æ, ¬“cˆê‹M, [£­H, ²“¡—F‹Å, gŽŸ¢‘ãŒ^ƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚̐݌v,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 103, 2011”N8ŒŽ.
  19. –ì‹v—º—S, [£­H, ²“¡—F‹Å, g‡˜‰ñ˜H‚̃EƒF[ƒu‰»‚ÉŠÖ‚·‚錤‹†,h •½¬23”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, pp. 116, 2011”N8ŒŽ.
  20. “àŠC°M, ÎŒ´‘ñ”ü, ŽO‘º’¼“¹, ‚–Ø—³Æ, ¬“cˆê‹M, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚ÌŠJ”­,h MŠw‹Z•ñ, vol. 111, no. 176, pp. 79-84, 2011”N8ŒŽ.
  21. “àŠC°M, ÎŒ´‘ñ”ü, ŽO‘º’¼“¹, ¬“cˆê‹M, ‚–Ø—³Æ, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚̃`ƒbƒvŠJ”­,h MŠw‹Z•ñ, vol. 110, no. 344, pp. 43-48, 2010”N12ŒŽ.
  22. ‚–Ø—³Æ, “àŠC°M, ÎŒ´‘ñ”ü, ä—Ñ, [£­H, ²“¡—F‹Å, gƒEƒF[ƒu‰»MFU‚ÌŠî–{ÝŒv€–Ú‚Ì•]‰¿,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 147, 2010”N8ŒŽ.
  23. ÎŒ´‘ñ”üC“àŠC°MC[£­HC²“¡—F‹Å, gƒXƒgƒŠ[ƒ€ƒTƒCƒtƒ@[ƒGƒ“ƒWƒ“‚̃`ƒbƒvŠJ”­,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 208, 2010”N8ŒŽ.
  24. ŽO‘º’¼“¹, “àŠC°M, ÎŒ´‘ñ”ü, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚Ì•]‰¿,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 146, 2010”N8ŒŽ.
  25. ¬“cˆê‹MCä—сCÎŒ´‘ñ”üC“àŠC°MC[£­HC²“¡—F‹Å, gƒNƒƒbƒNƒXƒL[ƒ€—Z‡Œ^ƒvƒƒZƒbƒTƒA[ƒLƒeƒNƒ`ƒƒ,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 148, 2010”N8ŒŽ.
  26. “àŠC°M, ÎŒ´‘ñ”ü, [£­H, ²“¡—F‹Å, gŽŸ¢‘ãŒ^ƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚ÌŠJ”­•]‰¿,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 282, 2010”N8ŒŽ.
  27. ¡³‰p, ꎓ¡Œ\‰î, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“‰»ƒtƒ@ƒCƒAƒEƒH[ƒ‹ƒ†ƒjƒbƒg‚Ì“d—Í•]‰¿,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 142, 2010”N8ŒŽ.
  28. ꎓ¡Œ\‰î, ²“¡—F‹Å, [£­H, gPacket Filtering Unit‚ÌŠJ”­,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 141, 2010”N8ŒŽ.
  29. ‘å‹÷—T‰î, [£­H, ²“¡—F‹Å, gStream cipher engine‚ÌŽŽìƒ`ƒbƒv‘ª’è,h •½¬22”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï—\eW, p. 281, 2010”N8ŒŽ.
  30. ˆÉŠÛ‰ªCÆ, ²“¡—F‹Å, [£­H, g”zü˜_—•ûŽ®ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^[ƒtƒF[ƒX‚ÌŠJ”­,h 2010”N“dŽqî•ñ’ʐMŠw‰ï‘‡‘å‰ïISS“Á•ÊŠé‰æŠw¶ƒ|ƒXƒ^[ƒZƒbƒVƒ‡ƒ“—\eWISS-P-142†, p. 42, 2010”N3ŒŽ.
  31. ÎŒ´‘ñ”ü, “àŠC°M, ‘å‹÷—T‰î, [£­H, ²“¡—F‹Å, gƒXƒgƒŠ[ƒ€ƒTƒCƒtƒ@[ƒGƒ“ƒWƒ“‚̃`ƒbƒvŠJ”­,h MŠw‹Z•ñ, vol. 109, pp. 336, pp. 95-100, 2009”N12ŒŽ.
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  38. ꎓ¡Œ\‰î, ˆÉ“¡Œd, ˆÉŠÛ‰ªCÆ, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“‰»ƒtƒ@ƒCƒAƒEƒH[ƒ‹ƒ†ƒjƒbƒg‚ÌFPGAŽÀ‘•,h MŠw‹Z•ñ, vol. 109, no. 171, pp. 83-88, pp. 77-81, 2009”N8ŒŽ.
  39. “àŠC°MCÎŒ´‘ñ”üC‘åŒG—T‰îC[£­HC²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒT‚̉ü—ǃEƒF[ƒu‰»,h •½¬21”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 109, 2009”N8ŒŽ.
  40. ˆÉ“¡Œd, ꎓ¡Œ\‰î, ˆÉŠÛ‰ªCÆ, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“‰»ƒtƒ@ƒCƒAƒEƒH[ƒ‹ƒ†ƒjƒbƒg‚Ì•]‰¿,h •½¬21”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 111, 2009”N8ŒŽ.
  41. ÎŒ´‘ñ”ü, “àŠC°M, ‘å‹÷—T‰î, [£­H, ²“¡—F‹Å, gStream Cipher Engine‚̉ü—Ç,h •½¬21”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 110, 2009”N8ŒŽ.
  42. [£­H, ‰¡ŽR‰·Žq, ‘åŒG—T‰î, ‘ºã—º•ã, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTƒ`ƒbƒv‚̐݌v‹Zp,h ƒAƒJƒfƒ~ƒbƒNƒvƒ‰ƒUEƒvƒƒOƒ‰ƒ€u‰‰˜_•¶W, pp. 17-23, 2009”N6ŒŽ.
  43. A. Yokoyama, K. Noda, M. Fukase and T. Sato, gA Waved MFU for a Ubiquitous Processor,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 38, 2008”N8ŒŽ.
  44. ‘ºã—º•ã, ‰¡ŽR‰·Žq, [£­H, ²“¡—F‹Å, g•‰‰×•ªŽUŒ^ŽŸ¢‘テƒrƒLƒ^ƒXƒVƒXƒeƒ€—p•À—ñ‰»ƒRƒ“ƒpƒCƒ‰,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 224, 2008”N8ŒŽ.
  45. ‘å‹÷—T‰î, –ì“cˆêŒP, [£­H, ²“¡—F‹Å, gStream cipher engine‚̐«”\•]‰¿,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 199, 2008”N8ŒŽ.
  46. ˆÉŠÛ‰ªCÆ, ²“¡—F‹Å, [£­H, gƒtƒ@ƒCƒ‹ŒðŠ·ƒ\ƒtƒgƒEƒFƒA‚ւ̃n[ƒhƒEƒFƒA‘Ώˆ,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 98, 2008”N8ŒŽ.
  47. ꎓ¡Œ\‰î, ˆÉŠÛ‰ªCÆ, ²“¡—F‹Å, [£­H, gƒlƒbƒgƒ[ƒNƒvƒƒZƒbƒT‚ÌŽÀ—p‰»‚ÉŠÖ‚·‚錤‹†,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 100, 2008”N8ŒŽ.
  48. K. Noda, A. Yokoyama, M. Fukase and T. Sato, gExploiting Double Hardware Cryptography,h •½¬20”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 39, 2008”N8ŒŽ.
  49. –ì“cˆêŒP, ‰¡ŽR‰·Žq, •“cGŽ÷, [£­H, ²“¡—F‹Å, gŽÀs’i‚Ì‘½‹@”\ƒEƒF[ƒu‰»‚É‚æ‚éƒ}ƒ‹ƒ`ƒƒfƒBƒA‹@”\‹­‰»,h MŠw‹Z•ñ, vol. 107, no. 508, pp. 7-12, 2008”N3ŒŽ.
  50. •“cGŽ÷, –ì“cˆêŒP, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTHCgorilla‚̉ü—Ç,h MŠw‹Z•ñ, vol. 107, no. 508, pp. 31-36, 2008”N3ŒŽ.
  51. ‹e’rˆê•½, ²“¡—F‹Å, [£­H, g•s³ƒAƒNƒZƒX–hŒäƒVƒXƒeƒ€‚̃n[ƒhƒEƒFƒAŽÀ‘•,h îˆŒ¤•ñ2007-CSEC, no. 39, pp. 13-18, 2007”N12ŒŽ.
  52. Šâ–{—SŒ°, “VŠÔ—», •“cGŽ÷, –ì“cˆêŒP, [£­H, ²“¡—F‹Å, gƒ}ƒ‹ƒ`ƒƒfƒBƒAƒXƒgƒŠ[ƒ€ˆÃ†ƒGƒ“ƒWƒ“,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 194, 2007”N8ŒŽ.
  53. ‰¡ŽR‰·Žq, •“cGŽ÷, –ì“cˆêŒP, [£­H, ²“¡—F‹Å, gHCgorilla‚̃n[ƒhƒEƒFƒA/ƒ\ƒtƒgƒEƒFƒA‹¦’²ÝŒv‚ÉŠÖ‚·‚錤‹†,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 189, 2007”N8ŒŽ.
  54. K. Noda, H. Takeda, M. Fukase and T. Sato, gMultimedia Performance of a Ubiquitous Processor,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 16, 2007”N8ŒŽ.
  55. •“cGŽ÷C–ì“cˆêŒPC[£­HC²“¡—F‹Å, gHCgorilla‚Ì‘å‹K–͉»‚ÉŠÖ‚·‚錤‹†,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 188, 2007”N8ŒŽ.
  56. ˆÉŠÛ‰ªCÆ, ¬“cŒ\ˆê, ‹e’rˆê•½, ²“¡—F‹ÅC[£­H, gWinny–hŒäƒ†ƒjƒbƒg‚ÌŽÀ—p‰»,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 107, 2007”N8ŒŽ.
  57. ‹e’rˆê•½, ²“¡—F‹Å, [£­H, gƒn[ƒhƒEƒFƒA‰»•s³ƒAƒNƒZƒX–hŒäƒVƒXƒeƒ€‚ÌŠJ”­,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 106, 2007”N8ŒŽ.
  58. ˆÉ“¡’qŒb”ü, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTHCgorilla—p•À—ñ‰»ƒRƒ“ƒpƒCƒ‰‚ÌŠJ”­Œ¤‹†,h •½¬19”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 98, 2007”N8ŒŽ.
  59. –ì“cˆêŒP, •“cGŽ÷, [£­H, ²“¡—F‹Å, gHCgorilla‚̃}ƒ‹ƒ`ƒƒfƒBƒA‹@”\‹­‰»,h îˆŒ¤•ñ, vol. 2007, no. 58, pp.85-90, 2007”N6ŒŽ.
  60. M. Fukase and T. Sato, gDesign Techniques of Wave Pipelines,h MŠw‹Z•ñ, ICD2007, vol. 28, pp. 67-72, 2007”N5ŒŽ.
  61. ‹e’rˆê•½, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“•ûŽ®PRNG‰ñ˜H‚Ì“®ìŒŸØ,h •½¬18”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ï, p. 208, 2006”N8ŒŽ.
  62. ²“¡—m•½, —«áû, [£­H, ²“¡—F‹Å, gHCgorilla‚É‚æ‚éƒn[ƒhƒEƒFƒAˆÃ†,h •½¬18”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 209, 2006”N8ŒŽ.
  63. ²“¡—º‘¾, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTHCgorilla—p•À—ñ‰»ƒRƒ“ƒpƒCƒ‰‚ÌŠJ”­,h •½¬18”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 265, 2006”N8ŒŽ.
  64. “n粗T‰î, [£­H, ²“¡—F‹Å, gƒ†ƒrƒLƒ^ƒXƒvƒƒZƒbƒTHCgorilla—pJavaƒCƒ“ƒ^[ƒtƒF[ƒX‚ÌŠJ”­,h •½¬18”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 266, 2006”N8ŒŽ.
  65. •“cGŽ÷, –ì“cˆêŒP, “VŠÔ—», [£­H, ²“¡—F‹Å, gƒ}ƒ‹ƒ`ƒƒfƒBƒAƒXƒgƒŠ[ƒ€ˆÃ†ƒGƒ“ƒWƒ“‚ÌŠJ”­,h •½¬18”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, p. 207, 2006”N8ŒŽ.
  66. R. Sakuma, D. Miyamori, M. Fukase and T. Sato, gDevelopment of a Security-Enforced Network Interface Card for Wireless LAN,h •½¬17”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, 2005”N8ŒŽ.
  67. R. Akaoka, M. Fukase and T. Sato, gHardware Cryptography-Embedded Multimedia Mobile Processor,h •½¬17”N“x“d‹CŠÖŒWŠw‰ï“Œ–kŽx•”˜A‡‘å‰ïu‰‰˜_•¶W, 2005”N8ŒŽ.
  68. M. Fukase, Y. Sato, Y. Nakamura, R. Akaoka and T. Sato, gHardware Cryptography-Embedded Multimedia Mobile Processor,h MŠw‹Z•ñ, vol. 104, no. 735, pp. 31-36, 2005”N3ŒŽ.
  69. T. Sato, R. Sakuma, D. Miyamori and M. Fukase, gSecurely Aware Design of a Power Conscious High-Speed Wireless LAN System,h MŠw‹Z•ñ, vol. 104, no. 735, pp.11-16, 2005”N3ŒŽ.
  70. ‹{X‘å•ã, ²‹vŠÔ—æ“Þ, ²“¡—F‹Å, [£­H, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“•ûŽ®CRC‰ñ˜H‚Ì•]‰¿,h •½¬15”N“x“d‹CŠÖŒWŠw‰ï–kŠC“¹Žx•”˜A‡‘å‰ïu‰‰˜_•¶W, 2003”N10ŒŽ.
  71. ŽO‘ŸŽu, ’†‘º‹gŽ÷, ¡ˆä—ç‘å, [£­H, ²“¡—F‹Å, gƒ‚ƒoƒCƒ‹ƒRƒ“ƒsƒ…[ƒeƒBƒ“ƒO—pƒ}ƒ‹ƒ`ƒƒfƒBƒAƒvƒƒZƒbƒT‚ÌŽÀ‘•,h î•ñˆ—Šw‰ï, FIT2003u‰‰˜_•¶W, 2003”N9ŒŽ.
  72. [£’©Žq, ²“¡—zˆê, ²“¡—F‹Å, [£­H, r–Ø‹ª, gƒ‰ƒ“ƒ_ƒ€ƒAƒhƒŒƒbƒVƒ“ƒO‹@”\‹­‰»Œ^ƒ}ƒ‹ƒ`ƒƒfƒBƒAƒvƒƒZƒbƒT‚É‚æ‚éˆÃ†ƒVƒXƒeƒ€,h î•ñˆ—Šw‰ï, FIT2003u‰‰˜_•¶W, 2003”N9ŒŽ.
  73. ²“¡—F‹Å, [£­H, ’†‘ºˆÛ’j, gƒEƒF[ƒuƒpƒCƒvƒ‰ƒCƒ“•ûŽ®ALU‚̐«”\•]‰¿,h MŠw‹Z–@, CPSY, vol. 100, no. 20, pp. 1-6, 2000”N4ŒŽ.
  74. Ž­–썂‰›C²“¡—F‹ÅC‰i“‡—SŽ÷C’·£’qsC[£­HC’†‘ºˆÛ’j, gATMƒlƒbƒgƒ[ƒN‚É‚¨‚¯‚éƒ|ƒCƒ“ƒgEƒc[Eƒ}ƒ‹ƒ`ƒ|ƒCƒ“ƒg‚Ì‚½‚߂̃XƒCƒbƒ`ƒA[ƒLƒeƒNƒ`ƒƒ,h ƒ}ƒ‹ƒ`ƒƒfƒBƒA’ʐM‚Æ•ªŽUˆ—ƒ[ƒNƒVƒ‡ƒbƒv, pp. 95-98, 1996”N10ŒŽ

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